Technical Field
Embodiments described herein relate to processors and more particularly, to utilizing caches in processors.
Description of the Related Art
Many modern computing devices (e.g., laptop/desktop computers, smart phones, set-top boxes, appliances, etc.) include processing subsystems with one or more caches. Caches are generally smaller, fast-access memory circuits located in or near the processing subsystem that can be used to store data that is retrieved from higher levels of a memory hierarchy in the computing device (i.e., other, larger caches and/or memories) to enable faster access to the stored data.
Generally, the main memory of a computer system has a memory organization at the page level of granularity. Typically, a page may be a four kilobyte (KB) page, although any other size page may be defined for a particular implementation. Cache memory organization is generally at a cacheline level of granularity. A cacheline is a set of bytes stored in contiguous memory locations, which are treated as a unit for coherency purposes. As used herein, each of the terms “cacheline” and “cache block” are interchangeable. The number of bytes in a cacheline may vary according to design choice, and may be of any size.
A multi-level cache hierarchy is often employed for modern processors. For example, for a multi-core processor, each core may include a level-one (L1) cache for storing data and/or instructions. The multi-level cache hierarchy would also typically include a private level-two (L2) cache per core and a larger level-three (L3) cache which is shared among the cores. The processor may execute many different types of applications which have different amounts of data to process and different data access patterns. Some applications may process large amounts of data while other applications may work with a small amount of data by progressively modifying the same portions of data. However, using the conventional multi-level cache hierarchy may result in some applications being executed by the processor at less than optimal efficiency.